
IDA Pro processor modules adding disassembly support for uncommon CPU, DSP, and GPU architectures including XMOS xCORE, TI C7x/PRU, MicroBlaze, and NVIDIA SASS.
A collection of processor modules extending IDA Pro with support for uncommon and specialized CPU, DSP, and GPU architectures.
These projects grew out of my interest in reverse engineering architectures that aren't natively supported by IDA, particularly those encountered in embedded systems, commercial firmware, and specialized computing hardware.
| Architecture | Description | Repository |
|---|---|---|
| XMOS xCORE | Event-driven multicore architecture used in embedded audio, USB, and real-time systems. | xcore-ida |
| TI C7x / C7000 | Advanced DSP architecture supporting parallel execution, vector operations, and specialized processing units. | c7x-ida |
| TI PRU / PRU-ICSS | Deterministic real-time processors used in industrial communication, automation, and embedded control. | pru-ida |
| AMD/Xilinx MicroBlaze | Configurable soft-core RISC processor used inside FPGA-based systems. | microblaze-ida |
| NVIDIA SASS | Native NVIDIA GPU machine-code architecture with generation-specific instruction encodings. | sass-ida |
Each architecture presents different reverse-engineering challenges, including:
Development has involved studying vendor documentation, examining real binaries, using reference disassemblers, and experimentally analyzing instruction encodings.
The goal is to make these architectures more accessible to researchers working with IDA.
I'm particularly interested in obscure, unusual, or under-supported processor architectures that appear in real-world firmware and executable binaries.
Good candidates typically have:
Have you encountered an architecture that IDA doesn't support but you wish it did?
Suggestions, technical discussions, and feedback are welcome.
Feel free to open a GitHub Discussion or Issue in the relevant repository.
Developed out of curiosity about unusual processor architectures and the challenges of reverse engineering them.