
riscv-isa-sim
Functional RISC-V ISA simulator supporting multiple extensions (RV32/64, V, cryptography) with interactive debug mode, GDB integration, and…

Functional RISC-V ISA simulator supporting multiple extensions (RV32/64, V, cryptography) with interactive debug mode, GDB integration, and…

A Java 8+ Jar & Android APK Reverse Engineering Suite (Decompiler, Editor, Debugger & More)

Multi-session IDALib MCP router for coding agents. Analyze multiple binaries in parallel with IDA-compatible reverse engineering tools.

Portable debugger-based crash triage tool for fuzzing outputs. Supports parallel triage, crash deduplication, sanitizer report parsing, and multiple…

Buffer overflow in FreeFloat FTP Server 1.0 illustrating how a single unsafe handler can generate multiple CVE entries across different commands.

Library for unwinding processor call stacks, supporting multiple architectures and operating systems, with build and regression testing instructions.

C library for stack unwinding and backtrace generation across multiple architectures, providing APIs for programmatic inspection of call stacks and…

C library for stack unwinding and backtrace generation, supporting multiple architectures and operating systems, with build and regression testing…

A libre cross-platform disassembler.

A reverse engineering framework written in Python.